Volumetric Evanescent Edge Coupling for Fiber-to-Chip Optical I/O

The 30-second take

• What: The authors propose volumetric edge coupling via TIR-mediated evanescent transfer through a 54.7° KOH-etched silicon sidewall and a wedged BOX ridge, simulating 88% (−0.56 dB) peak efficiency at 1550 nm and an 86.45 nm 1-dB C-band width.
• Abundance angle: today, dense optical I/O for co-packaged optics is scarce — one row of edge channels or fussy surface gratings that fight back-end metal. Area-scale perimeter coupling is a step toward cheaper default multi-fiber attach (mid-horizon: fabrication yield is the gate).
• Who should care: Silicon-photonics packaging teams, co-packaged-optics architects, and foundries that already KOH-etch 54.7° facets.

What the paper actually did

Scaling optical I/O for co-packaged optics is limited by the fiber-to-chip interface. Conventional edge coupling is low-loss and broadband but only along a single row on the facet. Surface couplers are often narrowband or hard to yield and compete with back-end metal routing.

The authors introduce volumetric edge coupling: the chip edge is structured in three dimensions so coupling happens over a 2D region, a route to many waveguides meeting many cores of a multicore fiber while still entering from the perimeter. They study a single-channel realization: total-internal-reflection-mediated evanescent coupling through the 54.7° sidewall of a KOH-etched silicon cavity, with the coupling profile set by a wedged buried-oxide ridge.

FDTD simulations predict 88% peak coupling (−0.56 dB) at 1550 nm and a 1-dB bandwidth of 86.45 nm across the C-band, plus about ±2 μm vertical alignment tolerance, weak sensitivity to 5 μm transverse offsets, and ±0.8° 1-dB angular tolerance. The reflected field is suggested as an alignment signal for future multicore attach.

What makes this disruptive

The scarce capability is many wideband optical channels that do not surrender the chip’s top metal or a whole facet row. A volumetric, perimeter, evanescent scheme — using a standard KOH angle — is a packaging-architecture attack, not another grating tooth.

Simulated C-band width and micron-scale alignment tolerances, plus a reflected alignment beacon, sketch a path to multicore I/O that edge and surface camps both want. That pressures the I/O bottleneck story in co-packaged optics.

It is a single-channel FDTD study, not a measured multi-core demonstrator.

Why it matters (outside the lab)

Abundance lens: cheap, dense optical I/O is how high-bandwidth compute becomes a default rather than a pluggable luxury. If volumetric edges work in silicon, more fibers per millimeter of perimeter can lower the cost of moving bits with light.

Near-term, this is a photonics design paper. Medium-term, etch yield, assembly, and reliability decide whether it is a default attach. No year when every GPU uses it.

Manufacturing is the gate.

Limitations & open questions

Results are FDTD predictions for one channel, not a fabricated, fiber-attached yield study. Peak 88% and 86.45 nm 1-dB BW are simulated. Multicore interfacing is a motivation, not a demonstrated array. Alignment tolerances are also simulated.

KOH 54.7° cavities and wedged BOX ridges have process risk not quantified here. Preprint ≠ qualified optical I/O. Abundance is not automatic: a clever facet does not demonetize co-packaged optics on a date.